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? semiconductor components industries, llc, 2017 november, 2017 ? rev. 2 1 publication order number: ncp1076a/d ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b enhanced off-line switcher for robust and highly efficient power supplies the ncp107xuz products integrate a fixed frequency current mode controller with a 700 v mosfet. available in a two different pin?out of the very common pdip?7 package, the ncp107xuz offers a high level of integration, including soft?start, frequency?jittering, short?circuit protection, skip?cycle, a maximum peak current set?point, ramp compensation, and a dynamic self?supply (dss, eliminating the need for an auxiliary winding). unlike other monolithic solutions, the ncp107xuz is quiet by nature: during nominal load operation, the part switches at one of the available frequencies (65, 100 or 130 khz). when the output power demand diminishes, the ic automatically enters frequency foldback mode and provides excellent efficiency at light loads. when the power demand reduces further, it enters into a skip mode to reduce the standby consumption down to a no load condition. protection features include: a timer to detect an overload or a short?circuit event, over?voltage protection with auto?recovery. ac input line voltage detection prevents lethal runaway in low input voltage conditions (brown?out) as well as too high an input line (ac line over?voltage protection). this also allows an over?power protection to compensate all internal delays in high input voltage conditions and optimize the maximum output current capability. for improved standby performance, the connection of an auxiliary winding stops the dss operation and helps to reduce input power consumption below 50 mw at high line. features ? built?in 700 v mosfet with r ds(on) of 13.5 (ncp1075uz), 4.8 (ncp1076uz/77uz) and 2.9 (ncp1079uz) ? large creepage distance between high voltage pins ? current?mode fixed frequency operation ? 65 / 100 / 130 khz ? various options for maximum peak current: see below table ? fixed slope compensation ? skip?cycle operation at low peak currents only ? dynamic self?supply: no need for an auxiliary winding ? internal 10 ms soft?start ? auto?recovery output short?circuit protection with timer?based detection ? auto?recovery over?voltage protection with auxiliary winding operation ? adjustable brown?out protection and ovp ? 2 nd leading edge blanking ? current protection (ncp107xua version only) ? over power protection ? frequency jittering for better emi signature ? no load input consumption < 50 mw ? frequency foldback to improve efficiency at light load ? these are pb?free devices typical applications ? auxiliary / standby isolated power supplies ? major home appliances power supplies ? power meter smps ? wide input industrial smps pdip?7 (pdip?8 less pin 6) case 626a marking diagrams www. onsemi.com x = power version (5, 6, 7, 9) u = pin connections (a, b) z = 2nd level ocp enabled/disabled (a, b) y = oscillator frequency 65, 100, 130 (a, b, c ) a = assembly location wl = wafer lot y, yy = year w, ww = work week g = pb?free package see detailed ordering and shipping information on page 31 o f this data sheet. ordering information p107xpuzy awl yywwg pdip?7 (pdip?8 less pin 3) case 626as p107xpuzy awl yywwg
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 2 pin connections gnd gnd gnd bo/ac_ovp fb drain vcc (top view) pdip?7 ncp107xa gnd gnd gnd bo/ac_ovp fb drain vcc (top view) pdip?7 ncp107xb pin function description pin no pin name function pin description pdip 7 a pdip 7 b 1 2 vcc ic supply pin this pin is connected to an external capacitor. the v cc management includes an auto?recov- ery over?voltage protection. 2 8 bo/ac_ovp brown?out / ac line over?voltage protection detects both input voltage conditions (brown? out) and too high an input voltage (ac line ovp). do not leave this pin floating ? if this pin is not used it should be directly connected do gnd. 3 5 gnd the ic ground 4 1 fb feedback signal input by connecting an opto?coupler to this pin, the peak current set?point is adjusted accordingly to the output power demand. 5 4 drain drain connection the internal drain mosfet connection 6 3 nc this un?connected pin ensures adequate creep- age distance 7 6 gnd the ic ground 8 7 gnd the ic ground products infos & indicative maximum output power product r ds(on) i pk 230 vrms 15% 85?265 vrms adapter open frame adapter open frame ncp1075uz 13.5 400 ma 8.5 w 14 w 6 w 10 w ncp1076uz / ncp1077uz 4.8 800 ma 19 w 31 w 14 w 23 w ncp1079uz 2.9 1050 ma 25 w 41 w 18 w 30 w note: informative values only, with t amb = 25 c, t case = 100 c, pdip?7 package, self?supply via auxiliary winding and circuit mounted on minimum copper area as recommended. quick selection table device frequency [khz] r ds(on) [ ] i pk [ma] package type ncp1075uz 65, 100, 130* 13.5 400 pdip?7 (pb?free) ncp1076uz 65, 100, 130* 4.8 650 ncp1077uz 65, 100, 130* 4.8 800 ncp1079uz 65, 100, 130* 2.9 1050 *note: 130 khz option available in pin connection b only
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 3 figure 1. typical isolated application (flyback converter), enable brown?out, ac line ovp and opp functions figure 2. typical isolated application (flyback converter), disabled brown?out function ? against line detection
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 4 figure 3. simplified internal circuit architecture bo/ac_ovp fb gnd drain vcc vcc management line detection r fb(up) tsd leb 1 soft?start current set?point i freeze i pk(0) line detection enable peak current protection ac ovp ac ovp i stop line detection enable bo enable bo enable brown?out opp slope compensation drv v fb(ref) sawtooth feedback control v cc ovp s r q i stop
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 5 maximum ratings table (all voltages related to gnd terminal) rating symbol value unit power supply voltage, vcc pin, continuous voltage v cc ?0.3 to 20 v voltage on all pins, except drain and vcc pin vinmax ?0.3 to 10 v drain voltage bv dss ?0.3 to 700 v maximum current into vcc pin i cc 15 ma drain current peak during transformer saturation (t j = 150 c): ncp1075uz ncp1076uz/77uz ncp1079uz drain current peak during transformer saturation (t j = 25 c): ncp1075uz ncp1076uz/77uz ncp1079uz i ds(pk) 0.9 2.2 3 . 6 1.5 3.9 6.4 a thermal resistance junction?to?air ? pdip7 0.36 sq. inch r j?a 77 c/w 1.0 sq. inch 68 maximum junction temperature t jmax 150 c storage temperature range ?60 to +150 c human body model esd capability (all pins except hv pin) per jedec jesd22?a114f hbm 2 kv human body model esd capability (drain pin) per jedec jesd22?a114f hbm 1 kv charged?device model esd capability per jedec jesd22?c101e cdm 1 kv machine model esd capability per jedec jesd22?a1 15?a mm 200 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. this device contains latch?up protection and exceeds 100 ma per jedec standard jesd78. 2. maximum drain current i ds(pk) is obtained when the transformer saturates. it should not be mixed with short pulses that can be seen at turn on. figure 4 below provides spike limits the device can tolerate. t < 1.5 x i ds(pk) i d (t) ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 6 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, v cc = 12 v unless otherwise noted) symbol rating pin min typ max unit supply section and vcc management v cc(on) v cc increasing level at which the switcher starts operation 1 (2) 8.0 8.4 8.9 v v cc(min) v cc decreasing level at which the hv current source restarts 1 (2) 6.5 6.9 7.3 v v cc(off) v cc decreasing level at which the switcher stops operation (uvlo) 1 (2) 6.1 6.5 6.9 v v cc(reset) v cc voltage at which the internal latch is reset (guaranteed by design) 1 (2) 4 v i cc1 internal ic consumption, mosfet switching (f sw = 65 khz) ncp1075uz ncp1076uz/77uz ncp1079uz 1 (2) ? ? ? 1.10 1.26 1.40 ? ? ? ma i cc(skip) internal ic consumption, v fb is 0 v (no switching on mosfet) 1 (2) ? 400 ? a power switch circuit r ds(on) power switch circuit on?state resistance (i drain = 50 ma) ncp1075uz t j = 25 c t j = 125 c ncp1076uz/77uz t j = 25 c t j = 125 c ncp1079uz t j = 25 c t j = 125 c 5 (4) ? ? ? ? ? ? 13.5 26.0 4.8 9.3 2.9 5.3 16.8 31.6 6.8 11.6 3.9 7.5 bv dss power switch circuit & start?up breakdown voltage (i drain(off) = 120 a, t j = 25 c) 5 (4) 700 ? ? v i dss(off) power switch & start?up breakdown voltage off?state leakage current t j = 125 c (v ds = 700 v) 5 (4) ? 85 ? a t r t f switching characteristics (r l = 50 , v ds set for i drain = 0.7 x i lim ) turn?on time (90% ? 10%) turn?off time (10% ? 90%) 5 (4) ? ? 20 10 ? ? ns internal start?up current source i start1 high?voltage current source, v cc = v cc(on) ? 200 mv 5 (4) 4.0 9.0 12.0 ma i start2 high?voltage current source, v cc = 0 v 5 (4) ? 0.5 ? ma v hv(min) minimum start?up voltage, v cc = 0 v 5 (4) ? 21 ? v v cc(th) v cc transient level for i start1 to i start2 toggling point 1 (2) ? 1.6 ? v current comparator i pk maximum internal current set?point at 50% duty?cycle fb pin open, t j = 25 c ncp1075uz ncp1076uz ncp1077uz ncp1079uz ? ? ? ? ? ? ? ? 400 650 800 1050 ? ? ? ? ma i pk(0) maximum internal current set?point at beginning of switching cycle fb pin open, bo/ac_ovp pin voltage 0.8 v, t j = 25 c ncp1075uz ncp1076uz ncp1077uz ncp1079uz ? ? ? ? 420 690 850 1110 470 765 940 1230 520 840 1030 1350 ma 3. the final switch current is: i pk(0) / (v in /l p + s a ) x v in /l p + v in /l p x t prop , with s a the built?in slope compensation, v in the input voltage, l p the primary inductor in a flyback, and t prop the propagation delay. 4. oscillator frequency is measured with disabled jittering.
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 7 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, v cc = 12 v unless otherwise noted) symbol unit max typ min pin rating current comparator i pksw(65) final switch current with a primary slope of 200 ma/ s, f sw = 65 khz (note 3) ncp1075uz ncp1076uz ncp1077uz ncp1079uz ? ? ? ? ? ? ? ? 450 710 860 1100 ? ? ? ? ma i pksw(100) final switch current with a primary slope of 200 ma/ s, f sw =100 khz (note 3) ncp1075uz ncp1076uz ncp1077uz ncp1079uz ? ? ? ? ? ? ? ? 440 685 825 1040 ? ? ? ? ma i pksw(130) final switch current with a primary slope of 200 ma/ s, f sw =130 khz (note 3) ncp1075uz ncp1076uz ncp1077uz ncp1079uz ? ? ? ? ? ? ? ? 450 685 820 1020 ? ? ? ? ma i pk(opp) maximum internal current set?point at beginning of switching cycle fb pin open, bo/ac_ovp pin voltage = 2.65 v, t j = 25 c ncp1075uz ncp1076uz ncp1077uz ncp1079uz ? ? ? ? ? ? ? ? 375 610 750 985 ? ? ? ? ma t ss soft?start duration (guaranteed by design) ? ? 10 ? ms t prop propagation delay from current detection to drain off state ? ? 100 ? ns t leb1 leading edge blanking duration 1 ? ? 300 ? ns t leb2 leading edge blanking duration 2 (ncp107xua version only) ? ? 100 ? ns internal oscillator f osc(65) oscillation frequency, 65 khz version, t j = 25 c (note 4) ? 59 65 71 khz f osc(100) oscillation frequency, 100 khz version, t j = 25 c (note 4) ? 90 100 110 khz f osc(130) oscillation frequency, 130 khz version, t j = 25 c (note 4) ? 117 130 143 khz f jitter frequency jittering in percentage of f osc ? ? 6 ? % f swing jittering modulation frequency ? ? 300 ? hz d max maximum duty?cycle ? 64 68 72 % feedback section i fb(fault) fb current for which fault is detected 4 (1) ? ?35 ? a i fb100% fb current for which internal current set?point is 100% (i pk(0) ) 4 (1) ? ?44 ? a i fb(freeze) fb current for which internal current set - point is i freeze 4 (1) ? ?90 ? a v fb(ref) equivalent pull?up voltage in linear regulation range (guaranteed by design) 4 (1) ? 3.3 ? v r fb(up) equivalent feedback resistor in linear regulation range (guaranteed by design) 4 (1) ? 19.5 ? k ? frequency foldback & skip i fbfold start of frequency foldback fb pin current level 4 (1) ? ?68 ? a i fbfold(end) end of frequency foldback fb pin current level, f sw = f min 4 (1) ? ?100 ? a 3. the final switch current is: i pk(0) / (v in /l p + s a ) x v in /l p + v in /l p x t prop , with s a the built?in slope compensation, v in the input voltage, l p the primary inductor in a flyback, and t prop the propagation delay. 4. oscillator frequency is measured with disabled jittering.
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 8 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, v cc = 12 v unless otherwise noted) symbol unit max typ min pin rating frequency foldback & skip f min the frequency below which skip?cycle occurs, t j = 25 c (note 4) ? 23 27 31 khz i fb(skip) the fb pin current level to enter skip mode 4 (1) ? ?120 ? a i freeze internal minimum current set?point (i fb = i fb(freeze) ) ncp1075uz ncp1076uz ncp1077uz ncp1079uz ? ? ? ? ? ? ? ? 165 270 330 430 ? ? ? ? ma slope compensation s a(65) the internal slope compensation @ 65 khz: ncp1075uz ncp1076uz ncp1077uz ncp1079uz ? ? ? ? ? ? ? ? 9 15 18 23 ? ? ? ? ma/ s s a(100) the internal slope compensation @ 100 khz: ncp1075uz ncp1076uz ncp1077uz ncp1079uz ? ? ? ? ? ? ? ? 14 23 28 36 ? ? ? ? ma/ s s a(130) the internal slope compensation @ 130 khz: ncp1075uz ncp1076uz ncp1077uz ncp1079uz ? ? ? ? ? ? ? ? 18 30 36 46 ? ? ? ? ma/ s protections t scp fault validation further to error flag assertion ? 35 48 ? ms t recovery off phase in fault mode ? ? 420 ? ms v ovp v cc voltage at which the switcher stops pulsing 1 (5) 17.0 18.0 18.8 v t ovp the filter of v cc ovp comparator ? ? 80 ? s v bo(en) brown?out level detection 2 (8) ? 50 ? mv v bo(on) brown?out level, the switcher starts pulsing, opp starts to decrease i pk 2 (8) 0.76 0.80 0.84 v v bo(hyst) brown?out hysteresis (guaranteed by design) 2 (8) ? 100 ? mv v acovp(on) ovp level when the switcher stops pulsing 2 (8) 2.755 2.900 3.045 v v acovp(off) ovp level when the switcher starts pulsing 2 (8) 2.3 2.6 2.9 v t bofilter v bo filter ? ? 20 ? s t bo brown?out timer ? ? 50 ? ms v hv(en) the drain pin voltage above which the mosfet operates. checked after one of the following events: tsd, uvlo, scp, or v cc ovp mode, bo/ac_ovp pin = 0 v 5 (4) 72 91 110 v i pk(150) high current protection, percent of max limit i pk (ncp107xua version only) ? ? 150 ? % temperature management tsd temperature shutdown (guaranteed by design) ? 150 ? ? c tsd hyst hysteresis in shutdown (guaranteed by design) ? ? 20 ? c 3. the final switch current is: i pk(0) / (v in /l p + s a ) x v in /l p + v in /l p x t prop , with s a the built?in slope compensation, v in the input voltage, l p the primary inductor in a flyback, and t prop the propagation delay. 4. oscillator frequency is measured with disabled jittering. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 9 typical characteristics figure 5. v cc(on) vs. temperature figure 6. v cc(min) vs. temperature temperature ( c) temperature ( c) 80 60 40 100 20 0 ?20 ?40 8.25 8.30 8.35 8.40 8.45 8.50 100 80 60 40 20 0 ?20 ?40 6.80 6.82 6.84 6.86 6.88 6.90 6.92 6.98 figure 7. v cc(off) vs. temperature figure 8. i dss(off) vs. temperature temperature ( c) temperature ( c) 80 60 40 120 20 0 ?20 ?40 6.42 6.45 6.48 6.46 6.47 6.49 80 60 120 40 20 0 ?20 ?40 30 50 60 80 110 120 130 figure 9. i cc1(1075uz) vs. temperature figure 10. i cc1(1076uz/77uz) vs. temperature temperature ( c) temperature ( c) 80 60 40 100 20 0 ?20 ?40 1.00 1.02 1.08 1.06 80 100 60 40 20 0 ?20 ?40 1.18 1.20 1.22 1.24 v cc(on) (v) v cc(min) (v) v cc(off) (v) i dss(off) ( a) i cc1(1075uz) (ma) i cc1(1076uz/77uz) (ma) 120 120 100 100 90 120 120 6.78 6.94 6.96 6.43 6.44 100 70 40 1.04 1.10 1.12 1.14 1.16 1.26 1.28 1.19 1.21 1.23 1.25 1.27
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 10 typical characteristics figure 11. i cc1(1079uz) vs. temperature figure 12. i pk(0)1075uz vs. temperature temperature ( c) temperature ( c) 80 60 100 40 20 0 ?20 ?40 1.21 1.27 1.29 1.31 1.33 1.39 100 80 60 40 20 0 ?20 ?40 420 430 450 460 figure 13. i pk(0)1076uz vs. temperature figure 14. i pk(0)1077uz vs. temperature temperature ( c) temperature ( c) 80 60 100 40 20 0 ?20 ?40 680 700 740 780 100 80 60 40 20 0 ?20 ?40 840 860 880 900 920 960 i cc1(1079uz) (ma) i pk(0)1075uz (ma) i pk(0)1076uz (ma) i pk(0)1077uz (ma) figure 15. i pk(0)1079uz vs. temperature figure 16. i start1 vs. temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 1000 1040 1080 1120 1160 1200 80 60 40 100 20 0 ?20 ?40 0 2 4 6 8 10 12 i pk(0)1079uz (ma) i start1 (ma) 440 120 120 120 720 760 120 120 120 940 1.35 1.37 1.25 1.23
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 11 typical characteristics figure 17. i start2 vs. temperature figure 18. r ds(on) vs. temperature temperature ( c) temperature ( c) 80 60 100 40 20 0 ?20 ?40 0.25 0.30 0.50 0.45 0.35 0.40 0.65 100 80 60 40 20 0 ?20 ?40 0 5 10 20 25 30 figure 19. f osc65 vs. temperature figure 20. f osc100 vs. temperature temperature ( c) temperature ( c) 80 60 120 40 20 0 ?20 ?40 60 62 64 66 100 80 60 40 20 0 ?20 ?40 91 94 96 97 99 i start2 (ma) r ds(on) ( ) f osc65 (khz) f osc100 (khz) figure 21. f osc130 vs. temperature temperature ( c) 120 80 60 40 20 0 ?20 ?40 119 121 125 131 f osc130 (khz) 15 120 120 ncp1075uz ncp1079uz ncp1076uz/77uz 120 95 98 100 63 65 100 0.60 0.55 61 93 92 127 figure 22. d max vs. temperature temperature ( c) 120 80 60 40 20 0 ?20 ?40 67.1 67.2 67.3 67.5 d max (%) 100 67.4 123 129
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 12 typical characteristics temperature ( c) temperature ( c) 80 60 100 40 20 0 ?20 ?40 350 355 360 365 370 375 380 100 80 60 40 20 0 ?20 ?40 47 48 49 50 51 52 temperature ( c) temperature ( c) 80 60 100 40 20 0 ?20 ?40 17.9 18.0 18.2 18.4 100 80 60 40 20 0 ?20 ?40 86 87 89 90 91 92 t recovery (ms) t scp (ms) v ovp (v) v hv(en) (v) temperature ( c) 120 80 60 40 20 0 ?20 ?40 0.785 0.790 0.795 0.800 0.805 0.810 v bo(on) (v) 120 120 120 120 18.1 18.3 100 88 figure 23. f min vs. temperature temperature ( c) 80 60 40 100 20 0 ?20 ?40 26.0 26.5 27.0 27.5 28.0 f min (khz) 120 figure 24. t recovery vs. temperature figure 25. t scp vs. temperature figure 26. v ovp vs. temperature figure 27. v hv(en) vs. temperature figure 28. v bo(on) vs. temperature
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 13 typical characteristics figure 29. v acovp(on) vs. temperature temperature ( c) 80 60 40 120 20 0 ?20 ?40 2.85 2.89 2.91 2.95 2.97 2.99 v acovp(on) (v) 100 2.93 2.87 figure 30. v acovp(off) vs. temperature temperature ( c) 80 60 100 40 20 0 ?20 ?40 2.590 2.595 2.600 2.610 2.615 2.620 v acovp(off) (v) 120 2.605 figure 31. bv dss /bv dss (25 c) vs. temperature temperature ( c) 120 80 60 40 20 0 ?20 ?40 0.925 0.950 1.025 1.100 bv dss /bv dss (25 c) [?] 1.000 100 0.975 1.050 1.075 figure 32. drain current peak during transformer saturation vs. junction temperature temperature ( c) 80 60 120 40 20 0 ?20 ?40 0 2 6 10 i ds(pk) (a) ncp1075uz ncp1079uz ncp1076uz/77uz 100 4 8 140 figure 33. i cc1 vs. v cc v cc (v) 14 13 17 12 11 9 8 7 1.0 1.1 1.4 1.7 i cc1 (ma) ncp1075uz ncp1079uz ncp1076uz/77uz 15 1.3 1.5 10 16 1.2 1.6
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 14 application information introduction thanks to on semiconductor very high voltage integrated circuit technology, the circuit hosts a high?voltage power mosfet featuring a 13.5/4.8/2.9 r ds(on) ? t j = 25 c. an internal current source delivers the start?up current, necessary to crank the power supply. ? current?mode operation: the controller uses current?mode control architecture. ? 700 v power mosfet: thanks to on semiconductor very high voltage integrated circuit technology, the circuit hosts a high?voltage power mosfet featuring a 4.8 and 2.9 r ds(on) ? t j = 25 c. this value lets the designer build a power supply up to 28 w operated on universal mains. an internal current source delivers the start?up current, necessary to crank the power supply. ? dynamic self?supply: this device could be used in an application without an auxiliary winding to provide supply voltage via an internal high?voltage current source. ? short?cir cuit protection: by permanently monitoring the feedback line activity, the ic is able to detect the presence of a short?circuit, immediately reducing the output power for a total system protection. a t scp timer is started as soon as the feedback current is below threshold, i fb(fault) , which indicates a maximum peak current condition. if at the end of this timer the fault is still present, then the device enters a safe, auto?recovery burst mode, affected by a fixed timer recurrence, t recovery . once the short has disappeared, the controller resumes and goes back to normal operation. ? built?in vcc over?v oltage protection: when the auxiliary winding is used to bias the vcc pin (no dss), an internal comparator is connected to vcc pin. in case the voltage on the pin exceeds the v ovp level (18 v typically), the controller immediately stops switching and awaits a full timer period (t recovery ) before attempting to re?start. if the fault is gone, the controller resumes operation. if the fault is still there, e.g. in the case of a broken opto?coupler, the controller protects the load through a safe burst mode. ? line detection: an internal comparator monitors the drain voltage. if the drain voltage is lower than the internal threshold (v hv(en) ), the internal power switch is inhibited. this avoids operating at too low an ac input. line detection is active, when bo/ac_ovp pin is grounded. ? brown?out detection and ac line over?voltage protection: the bo/ac_ovp input monitors bulk voltage level via resistive divider and thus assures that the application is working only for designed bulk voltage. when bo/ac_ovp pin is connected to ground, line detection is inhibited. ? internal opp: an internal function using the bulk voltage to program the maximum current reduction for a given input voltage. internal opp is active when bo/ac_ovp pin is connected via resistive divider to the bulk voltage. ? 2 nd leb (ncp107xua only): second level of current protection. if peak current is 150% max peak current limit, then the controller stops switching after three pulses and waits for an auto?recovery period (t recovery ) before attempting to re?start. ? frequency jittering: an internal low?frequency modulation signal varies the pace at which the oscillator frequency is modulated. this helps spreading out energy in conducted noise analysis. to improve the emi signature at low power levels, the jittering remains active in frequency foldback mode. ? soft?start: a 10 ms soft?start ensures a smooth start?up sequence, reducing output overshoots. ? frequency foldback capability: a continuous flow of pulses is not compatible with no?load/light?load standby power requirements. to excel in this domain, the controller observes the feedback current information and when it reaches a level of i fbfold , the oscillator then starts to reduce its switching frequency as the feedback current continues to increase (the power demand continues to reduce). it can go down to 27 khz (typical) reached for a feedback level of i fbfold(end) (100 a roughly). at this point, if the power continues to drop, the controller enters classical skip?cycle mode. ? skip: if smps naturally exhibits a good efficiency at nominal load, they begin to be less efficient when the output power demand diminishes. by skipping un?needed switching cycles, the ncp107xuz drastically reduces the power wasted during light load conditions.
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 15 start?up sequence when the power supply is first powered from the mains outlet, the internal current source (typically 9.2 ma) is biased and charges up the v cc capacitor from the drain pin. once the voltage on this v cc capacitor reaches the v cc(on) level (typically 8.4 v), the current source turns off and pulses are delivered by the output stage: the circuit is awake and activates the power mosfet if the bulk voltage is above v hv(en) level (brown?in protection) or voltage on bo/ac_ovp pin is above v bo(on) level (brown?out protection). figure 34 details the simplified internal circuitry. being loaded by the circuit consumption, the voltage on the v cc capacitor goes down. when v cc is below v cc(min) level (7 v typically), it activates the internal current source to bring v cc toward v cc(on) level and stops again: a cycle takes place whose low frequency depends on the v cc capacitor and the ic consumption. a 1.5 v ripple takes place on the vcc pin whose average value equals (v cc(on) + v cc(min) )/2. figure 35 portrays a typical operation of the dss. r limit drain i start 1 gnd v cc (on ) v cc (min ) v ovp c vcc vcc v bulk i cc 1 i 2 i 1 figure 34. the internal arrangement of the start?up circuitry figure 35. the charge / discharge cycle over a 1 f v cc capacitor 0 1 2 3 4 5 6 7 8 9 012345678 v [v] time [ms] v cc 8.4 v v cc(th) startup duration device internal pulses 6.9 v
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 16 as one can see, even if there is auxiliary winding to provide energy for v cc , it happens that the device is still biased by dss during start?up time or some fault mode when the voltage on auxiliary winding is not ready yet. the v cc capacitor shall be dimensioned to avoid v cc crosses v cc(off) level, which stops operation. the v between v cc(min) and v cc(off) is 0.5 v. there is no current source to charge v cc capacitor when driver is on, i.e. drain voltage is close to zero. hence the v cc capacitor can be calculated using c vcc i cc1 d max f osc v (eq. 1) take the 65 khz device as an example. c vcc should be above c vcc 1.45 10 ?3 0.73 59 10 3 0.5 36 nf a margin that covers the temperature drift and the voltage drop due to switching inside fet should be considered, and thus a capacitor above 0.1 f is appropriate. the v cc capacitor has only a supply role and its value does not impact other parameters such as fault duration or the frequency sweep period for instance. as one can see on figure 34, an internal ovp comparator protects the switcher against lethal v cc runaways. this situation can occur if the feedback loop opto?coupler fails, for instance, and you would like to protect the converter against an over?voltage event. in that case, the over?voltage protection (ovp) circuit immediately stops the output pulses for t recovery duration (420 ms typically). then a new start?up attempt takes place to check whether the fault has disappeared or not. the ovp paragraph gives more design details on this particular section. fault condition ? short?circuit on vcc in some fault situations, a short?circuit can purposely occur between v cc and gnd. in high line conditions (v hv = 370 v dc) the current delivered by the start?up device will seriously increase the junction temperature. for instance, since i start1 equals 4.9 ma (the min corresponds to the highest t j ), the device would dissipate 370 x 4.9 x 10 ?3 = 1.81 w. to avoid this situation, the controller includes a novel circuitry made of two start?up levels, i start1 and i start2 . at power?up, as long as v cc is below a 1.6 v level, the source delivers i start2 (around 500 a typical), then, when v cc reaches 1.6 v, the source smoothly transitions to i start1 and delivers its nominal value. as a result, in case of short?circuit between v cc and gnd, the power dissipation will drop to 370 x 500 x 10 ?6 = 185 mw. figure 35 portrays this particular behavior. the first start?up period is calculated by the formula c x v = i x t, which implies a 1 x 10? 6 x 1.6 / (500 x 10? 6 ) = 3.2 ms start?up time for the first sequence. the second sequence is obtained by toggling the source to 8.9 ma with a v of v cc(on) ? v cc(th) = 8.4 v ? 1.6 v = 6.8 v, which finally leads to a second start?up time of 1 x 10? 6 x 6.8 / (8.9 x 10? 3 ) = 0.76 ms. the total start?up time becomes 3.2 ms + 0.76 ms = 3.96 ms. please note that this calculation is approximated by the presence of the knee in the vicinity of the transition. fault condition ? output short?circuit as soon as v cc reaches v cc(on) , drive pulses are internally enabled. if everything is correct, the auxiliary winding increases the voltage on the vcc pin as the output voltage rises. during the start?sequence, the controller smoothly ramps up the peak drain current to maximum setting, i.e. i pk , which is reached after a typical period of 10 ms. when the output voltage is not regulated, the current coming through fb pin is below i fbfault level (35 a typically), which is not only during the start?up period but also anytime an overload occurs, an internal error flag is asserted, i pflag , indicating that the system has reached its maximum current limit set?point. the assertion of this flag triggers a fault counter t scp (48 ms typically). if at counter completion, i pflag remains asserted, all driving pulses are stopped and the part stays off in t recovery duration (about 420 ms). a new attempt to re?start occurs and will last 48 ms providing the fault is still present. if the fault still affects the output, a safe burst mode is entered, affected by a low duty?cycle operation (11%). when the fault disappears, the power supply quickly resumes operation. figure 36 depicts this particular mode:
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 17 figure 36. in case of short?circuit or overload, the ncp107xuz protects itself and the power supply via a low frequency burst mode. the v cc is maintained by the current source and self?supplies the controller. drv internal 420 ms typ. fault level 48 ms typ. timer v cc v cc(min) v cc(on) v fb i pflag open loop fb auto?recovery over?voltage protection the particular ncp107xuz arrangement offers a simple way to prevent output voltage runaway when the opto?coupler fails. as figure 37 shows, a comparator monitors the vcc pin. if the auxiliary winding delivers too much voltage to the c vcc capacitor, then the controller considers an ovp situation and stops the internal drivers. when an ovp occurs, all switching pulses are permanently disabled. after t recovery delay, the circuit resumes operations. if the failure symptom still exists, e.g. feedback opto?coupler fails, the device keeps the auto?recovery ovp mode. we recommend the insertion of a resistor ( r limit ) between the auxiliary dc level and the vcc pin to protect the ic against high voltage spikes, which can damage the ic. it is also recommended to filter out the vcc line to avoid undesired ovp activations. r limit should be carefully selected to suppress false?triggers of the ovp as we discussed, but also to avoid disturbing the v cc in low / light load conditions. self?supplying controllers in extremely low?standby applications often puzzles th e designer. actually, if a smps operated at nominal load can deliver an auxiliary voltage of an arbitrary 16 v (v nom ), this voltage can drop below 10 v (v stby ) when entering standby. this is because the recurrence of the switching pulses expands so much that the low frequency re?fueling rate of the v cc capacitor is not enough to keep a proper auxiliary voltage. v ovp gnd vcc drain shut down internal drv 80 s filter v cc (on ) =8.4v v cc (min ) =6.9v i start 1 r limit d1 c vcc c aux n aux figure 37. a more detailed view of the ncp107xuz offers better insight on how to properly wire an auxiliary winding
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 18 figure 38. describes the main signal variations when the part operates in auto?recovery ovp v cc i fb timer drv internal v cc(min) v cc(on) v ovp fault level 48 ms typ. 420 ms typ. soft?start the ncp107xuz features a 10 ms soft?start which reduces the power?on stress but also contributes to lower the output overshoot. soft?start is running every time when ic starts switching. it means a first start, a new start after ovp, tsd, brown?out, etc. figure 39 shows a typical operating waveform. the ncp107xuz features a novel patented structure which offers a better soft?start ramp, almost ignoring the start?up pedestal inherent to traditional current?mode supplies: drain current v cc v cc(on) max i pk 10 ms 0v (fresh pon) figure 39. the 10 ms soft?start sequence
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 19 jittering frequency jittering is a method used to soften the emi signature by spreading the energy in the vicinity of the main switching component. the ncp107xuz offers a 6% deviation of the nominal switching frequency. the sweeping sawtooth is internally generated and modulates the clock up and down with a fixed frequency of 300 hz. figure 40 shows the relationship between the jitter ramp and the frequency deviation. it is not possible to externally disable the jitter. 65 khz 68.9 khz 61.1 khz jitter ramp internal sawtooth adjustable figure 40. modulation effects on the clock signal by the jittering sawtooth line detection when bo/ac_ovp pin is grounded (voltage on this pin is below v bo(en) ) figure 2, then an internal comparator monitors the drain voltage as recovering from one of the following situations: ? short?circuit protection, ? v cc ovp is confirmed, ? uvlo ? tsd if the drain voltage is lower than the internal threshold v hv(en) (91 v dc typically), the internal power switch is inhibited. this avoids operating at too low ac input. brown?out function, ac line over?voltage protection the brown?out circuitry offers a way to protect the application from operation under too low an input voltage. below a given level, the controller blocks the output pulses, above it, it authorizes them. the internal circuitry, depicted by figure 41, offers a way to observe the high?voltage (hv) rail. figure 41. the internal brown?out configuration bo/ac_ovp v bo(on) v bo(en) line detection disable bo enable v ac(ovp) ac ovp 20 s filter 20 s filter 20 s filter r upper r lower v bulk c bo t bo
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 20 a resistive divider made of r upper and r lower, brings a portion of the hv rail on bo/ac_ovp pin. below the v bo(en) = 50 mv is the brown?out function disabled, over the v bo(en) brown?out function is enable and against line detection is inhibited. if voltage on bo/ac_ovp pin is higher than v bo(on) , switcher starts pulsing. if voltage falls down under v bo(off) ? level v bo(on) minus v bo(hyst) , the switcher waits 50 ms and then stops pulsing, depicted by figure 42. bulk voltage at which ic starts switching is set by resistive divider. figure 42. brown?out input functionality with 50 ms timer v bo(off) v bo(on) v cc v bo/ac_ovp drv internal v cc(min) v cc(on) timer 50 ms 50 ms
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 21 the ic also includes over?voltage protection. if the voltage on bo/ac_ovp pin exceed v acovp(on) , the switcher immediately stops pulsing until the voltage on bo/ac_ovp pin drops under v acovp(off) , depicted by figure 43. v avovp(off) v acovp(on) v bo(off) v bo(on) v cc v bo/ac_ovp drv internal v cc(min) v cc(on) figure 43. brown?out input functionality with ac line ovp function calculation of the resistive divider: r lower r upper v bo(on) v bulk v bo(on) (eq. 2) if we decide to start pulsing at v bulk(on) = 113 v dc (80 v rms at ac mains): r lower r upper v bo(on) v bulk(on) v bo(on) 0.8 113 0.8 7.1 m we choose r lower = 100 k r upper 100 10 3 7.1 10 ?3 14 m then power losses on resistive divider for worst case (v bulk = 409 v dc) p u i u 2 r u 2 r upper r lower 409 2 14 10 6 100 10 3 12 mw (eq. 3) for v bulk(on) = 113 v dc will be over?voltage protection (voltage when the switcher stops pulsing): v bulk(ovp) v acovp(on) r lower r upper r lower v acovp(on) v bulk(on) v bo(on) 29 113 0.8 409 vdc 290 vrms (eq. 4)
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 22 v bo(off) v bo(on) v cc v b o/ac_ovp drain current v cc(min) v cc(on) timer 50 ms soft?start soft? start figure 44. brown?out functionality in soft?start if voltage on vcc pin is higher than v cc(on) and voltage on bo/ac_ovp pin is higher than v bo(on) then ic starts pulsing, drain current is increasing for 10 ms (soft?start). brown?out is inhibited during soft?start, when soft?start ended, brown?out checked if is voltage on bo/ac_ovp pin higher than v bo(off) . if the voltage is lower, timer count 50 ms and if the voltage don?t increase over v bo(off) then ic stops switching as one can see on figure 44. frequency foldback the reduction of no?load standby power associated with the need for improving the ef ficiency, requires to change the traditional fixed?frequency type of operation. this device implements a switching frequency folback when the feedback current passes above a certain level, i fbfold , set around 68 a. at this point, the oscillator enters frequency foldback and reduces its switching frequency. the internal peak current set?point is following the feedback current information until its level reaches the minimal freezing level point of i freeze . below this value, the peak current set?point is frozen to 30% of the i pk(0) . the only way to further reduce the transmitted power is to diminish the operating frequency down to f min (27 khz typically). this value is reached at a feedback current level of i fbfold(end) (100 a typically). below this point, if the output power continues to decrease, the part enters skip cycle for the best noise?free performance in no?load conditions. figures 45 and 46 depict the adopted scheme for the part.
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 23 figure 45. by observing the current on the fb pin, the controller reduces its switching frequency for an improved performance at light load 0 20 40 60 80 100 120 140 50 60 70 80 90 100 frequency [khz] i fb [ a] 130 khz 100 khz 65 khz figure 46. i pk set?point is frozen at lower power demand 0 200 400 600 800 1000 1200 1400 40 50 60 70 80 90 100 110 current set point [ma] i fb [ a] ncp1079uz ncp1077uz ncp1076uz ncp1075uz feedback and skip the fb pin operates linearly as the absolute value of feedback current (i fb ) is above 40 a. in this linear operating range, the dynamic resistance is 19.5 k typically (r fb(up) ) and the effective pull up voltage is 3.3 v typically (v fb(ref) ). when i fb is decreased, the fb voltage will increase to 3.3 v.
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 24 figure 47 depicts the skip mode block diagram. when the fb current information reaches i fb(skip) , the internal clock to set the flip?flop is blanked and the internal consumption of the controller is decreased. the hysteresis of internal skip comparator is minimized to lower the ripple of the auxiliary voltage for vcc pin and v out of power supply during skip mode. it easies the design of v cc overload range. osc jittering foldback i fb (skip ) r fb (up ) v fb (ref ) s r q cs comparator fb skip drv stage figure 47. skip cycle schematic over?power protection this function lets you limit the maximum dc output current regardless of the operating input voltage. for a correct operation, the bo/ac_ovp pin must be connected via a resistive divider to observe the bulk voltage. s r q i fb to cs setpoint i freeze i pk(0) vramp + vsense osc i fb mosfet r upper r lower v bulk bo/ac_ovp 2.65 v v bo (on ) i pk (0) i pk (opp ) figure 48. the opp circuity affects the maximum peak current set?point in relationship to the input voltage.
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 25 figure 49. current set?point dependence on bo/ac_ovp pin voltage 300 400 500 600 700 800 900 1000 1100 1200 1300 0 0.5 1.0 1.5 2.0 2.5 3.0 max current set-point [ma] v bo/acovp [v ] ncp1079uz ncp1077uz ncp1076uz ncp1075uz there are several known ways to implement over?power protection (opp), all suffering from particular problems. these problems range from the added consumption burden on the converter or the skip?cycle disturbance brought by the current?sense of fset. in this case is added consumption due to resistive divider (equation 2). maximum peak current is reduced internally according to bulk voltage. when v bo(opp) is maximum, the peak current set?point is reduced by 10%. bulk voltage at which will be maximum current peak reduced by 20% (10% in ncp1075uz): v bulk(opp) v bo(opp) v bulk(on) v bo(on) v bo(opp) r lower r upper r lower 2.65 100 10 3 14 10 6 100 10 3 375 vdc 265 vrms (eq. 5)
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 26 second leb ? peak current protection (ncp107xua only) there is a second level of current protection with 100 ns propagation delay to prevent ic against high peak current. if peak current is 150% max peak current limit, then the controller stops switching after three pulses and waits for an auto?recovery period (t recovery ) before attempting to re?start. slope compensation and i pk set?point in order to let the ncp107xuz operate in ccm with a duty?cycle above 50%, a fixed slope compensation is internally applied to the current?mode control. below appears a table of the slope compensation level, the initial current set?point, and the final current set?point of different versions of switcher. ncp1075uz ncp1076uz ncp1077uz ncp1079uz f sw [khz] 65 100 130 65 100 130 65 100 130 65 100 130 s a [ma/ s] 9 14 18 15 23 30 18 28 36 24 37 46 i pk (duty?cycle = 50%) [ma] 400 600 800 1050 i pk(0) [ma] 470 765 940 1230 figure 50 depicts the variation of i pk set?point vs. the power switcher duty ratio, which is caused by the internal ramp compensation. figure 50. i pk set?point varies with power switch on time, which is caused by the ramp compensation 0 200 400 600 800 1000 1200 1400 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 i ipk set-point [ma] duty ratio [%] ncp1079uz ncp1077uz ncp1076uz ncp1075uz
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 27 design procedure the design of an smps around a monolithic device does not differ from that of a standard circuit using a controller and a mosfet. however, one needs to be aware of certain characteristics specific of monolithic devices. let us follow the steps: v in,min = 90 v rms or 127 v dc once rectified, assuming a low bulk ripple v in,max = 265 v rms or 375 v dc v out = 12 v p out = 10 w operating mode is ccm = 0.8 1. the lateral mosfet body?diode shall never be forward biased, either during start?up (because of a large leakage inductance) or in normal operation, depicted by figure 51. this condition sets the maximum voltage that can be reflected during t f as a result, the flyback voltage which is reflected on the drain at the switch opening cannot be larger than the input voltage. when selecting components, you thus must adopt a turn ratio which adheres to the following equation: n v out v f
v in,min (eq. 6) 2. in our case, since we operate from a 127 v dc rail while delivering 12 v, we can select a reflected voltage of 120 v dc maximum. therefore, the turn ratio np:ns must be smaller than v reflect v out v f 120 12 0.5 9.6ornp:ns 9.6 here we choose n = 8 in this case. we will see later on how it affects the calculation. figure 51. the drain?source wave shall always be positive i peak i valley i avg i lavg dt sw t sw i l t i l figure 52. primary inductance current evolution in ccm 3. lateral mosfets have a poorly doped body?diode which naturally limits their ability to sustain the avalanche. a traditional rcd clamping network shall thus be installed to protect the mosfet. in some low power applications, a simple capacitor can also be used since v drain,max (eq. 7) v in n v out v f
i peak l f c tot where l f is the leakage inductance, c tot the total capacitance at the drain node (which is increased by the capacitor you will wire between drain and source), n the n p :n s turn ratio, v out the output voltage, v f the secondary diode forward drop and finally, i peak the maximum peak current. worse case occurs when the smps is very close to regulation, e.g. the v out target is almost reached and i peak is still pushed to the maximum. for this
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 28 design, we have selected our maximum voltage around 650 v (at v in = 375 v dc). this voltage is given by the rcd clamp installed from the drain to the bulk voltage. we will see how to calculate it later on. 4. calculate the maximum operating duty?cycle for this flyback converter operated in ccm: d max n v out v f
n v out v f
v in,min (eq. 8) 1 1 v in,min n (v out v f ) 0.44 5. to obtain the primary inductance, we have the choice between two equations: l v in d
2 f sw k p in (eq. 9) k i l i lavg (eq. 10) where and defines the amount of ripple we want in ccm, depicted by figure 51. ? small k: deep ccm, implying a large primary inductance, a low bandwidth and a large leakage inductance. ? large k: approaching dcm where the conduction losses are worse, but smaller inductance, leading to a better leakage inductance. from equation 9, a k factor of 1 (50% ripple), gives an inductance of: i l v in d l f sw 127 0.44 3.8 10 ?3 65 10 3 223 ma (eq. 11) l ( 127 0.44 ) 2 65 k 1 12.75 3.8 mh peak?to?peak the peak current can be evaluated to be: i peak i avg d i l 2 98 10 ?3 0.44 223 10 ?3 2 335 ma (eq. 12) on i l , i lavg can also be calculated i lavg i peak i l 2 335 10 ?3 223 10 ?3 2 223 ma (eq. 13) 6. based on the above numbers, we can now evaluate the conduction losses: i d,rms d i peak 2 i peak i l i l 2 3
0.44 0.335 2 0.335 0.223 0.223 2 3
154 ma (eq. 14) if we take the maximum r ds(on) for a 125 c junction temperature, i.e. 10.1 , then conduction losses worse case are: p cond i d,rms 2 r ds(on) 154 10 ?3
2 13.6 323 mw (eq. 15) 7. off?time and on?time switching losses can be estimated based on the following calculations: p off i peak (v bulk v clamp ) t f 2 t sw 0.335 (127 120 2) 10 10 ?9 2 15.4 10 ?6 40 mw (eq. 16) where, assume the v clamp is equal to 2 times of reflected voltage. p on i valley v bulk n (v out v f )
t r 6 t sw 0.112 (127 100) 20 10 ?9 6 15.4 10 ?6 5.5 mw (eq. 17) it is noted that the overlap of voltage and current seen on mosfet during turning on and off duration is dependent on the snubber and parasitic capacitance seen from drain pin. therefore the t f and t r in equations 16 and 17 have to be modified after measuring on the bench. 8. the theoretical total power is then p mosfet 323 40 5.5 368.5 mw 9. if the ncp107xuz operates at dss mode, then the losses caused by dss mode should be counted as losses of this device on the following calculation: p dss i cc1 v in,max 1.5 10 ?3 375 563 mw (eq. 18)
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 29 mosfet protection as in any flyback design, it is important to limit the drain excursion to a safe value, e.g. below the mosfet bv dss which is 700 v. figure 53 a?b?c present possible implementations: figure 53. different options to clamp the leakage spike figure 53a : the simple capacitor limits the voltage according to the lateral mosfet body?diode shall never be forward biased, either during start?up (because of a large leakage inductance) or in normal operation as shown by figure 51. this condition sets the maximum voltage that can be reflected during t f . as a result, the flyback voltage which is reflected on the drain at the switch opening cannot be larger than the input voltage. when selecting components, you must adopt a turn ratio which adheres to the following equation 6 . this option is only valid for low power applications, e.g. below 5 w, otherwise chances exist to destroy the mosfet. after evaluating the leakage inductance, you can compute c with (equation 7). typical values are between 100 pf and up to 470 pf. large capacitors increase capacitive losses... figure 53b : the most standard circuitry is called the rcd network. you calculate r clamp and c clamp using the following formulae: r clamp 2 v clamp v clamp (v out v f ) n
l leak i leak 2 f sw (eq. 19) c clamp v clamp v ripple f sw r clamp (eq. 20) v clamp is usually selected 50?80 v above the reflected value n x (v out + v f ) . the diode needs to be a fast one and a mur160 represents a good choice. one major drawback of the rcd network lies in its dependency upon the peak current. worse case occurs when i peak and v in are maximum and v out is close to reach the steady?state value. figure 53c : this option is probably the most expensive of all three but it offers the best protection degree. if you need a very precise clamping level, you must implement a zener diode or a tvs. there are little technology differences behind a standard zener diode and a tvs. however, the die area is far bigger for a transient suppressor than that of zener. a 5 w zener diode like the 1n5388b will accept 180 w peak power if it lasts less than 8.3 ms. if the peak current in the worse case (e.g. when the pwm circuit maximum current limit works) multiplied by the nominal zener voltage exceeds these 180 w, then the diode will be destroyed when the supply experiences overloads. a transient suppressor like the p6ke200 still dissipates 5 w of continuous power but is able to accept surges up to 600 w @ 1 ms. select the zener or tvs clamping level between 40 to 80 volts above the reflected output voltage when the supply is heavily loaded. as a good design practice, it is recommended to implement one of this protection to ensure a maximum drain pin voltage below 650 v (to have some margin between drain pin voltage and bv dss ) during most stringent operating conditions (high v in and peak power condition).
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 30 power dissipation and heatsinking the ncp107xuz welcomes two dissipating terms, the dss current?source (when active) and the mosfet. thus, p tot = p dss + p mosfet . it is mandatory to properly manage the heat generated by losses. if no precaution is taken, risks exist to trigger the internal thermal shutdown (tsd). to help dissipating the heat, the pcb designer must foresee large copper areas around the package. take the pdip?7 package as an example, when surrounded by a surface approximately 200 mm 2 of 35 m copper, the maximum power the device can thus evacuate is: p max t j(max) t amb(max) r ja (eq. 21) which gives around 1300 mw for an ambient of 50 c and a maximum junction of 150 c. if the surface is not large enough, the r ja is growing and the maximum power the device can evacuate decreases. figure 54 gives a possible layout to help drop the thermal resistance. figure 54. a possible pcb arrangement to reduce the thermal resistance junction?to?ambient bill of material: c 1 bulk capacitor, input dc voltage is connected to the capacitor c 2 , r 1 , d 1 clamping elements c 3 v cc capacitor ok 1 opto?coupler
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 31 ordering information device frequency [khz] r ds(on) [ ] i pk [ma] soft?start package type shipping ncp1075aap065g 65 13.5 400 enabled pdip8 (less pin#6) 50 units / rail ncp1075aap100g 100 13.5 400 enabled pdip8 (less pin#6) ncp1075bap065g 65 13.5 400 enabled pdip8 (less pin#3) ncp1075bap100g 100 13.5 400 enabled pdip8 (less pin#3) ncp1075bap130g 130 13.5 400 enabled pdip8 (less pin#3) NCP1076AAP065G 65 4.8 650 enabled pdip8 (less pin#6) ncp1076aap100g 100 4.8 650 enabled pdip8 (less pin#6) ncp1076bap065g 65 4.8 650 enabled pdip8 (less pin#3) ncp1076bap100g 100 4.8 650 enabled pdip8 (less pin#3) ncp1076bap130g 130 4.8 650 enabled pdip8 (less pin#3) ncp1077aap065g 65 4.8 800 enabled pdip8 (less pin#6) ncp1077aap100g 100 4.8 800 enabled pdip8 (less pin#6) ncp1077bap065g 65 4.8 800 enabled pdip8 (less pin#3) ncp1077bap100g 100 4.8 800 enabled pdip8 (less pin#3) ncp1077bap130g 130 4.8 800 enabled pdip8 (less pin#3) ncp1079aap065g 65 2.9 1050 enabled pdip8 (less pin#6) ncp1079aap100g 100 2.9 1050 enabled pdip8 (less pin#6) ncp1079bap065g 65 2.9 1050 enabled pdip8 (less pin#3) ncp1079bap100g 100 2.9 1050 enabled pdip8 (less pin#3) ncp1079bap130g 130 2.9 1050 enabled pdip8 (less pin#3) ncp1075abp065g 65 13.5 400 disabled pdip8 (less pin#6) ncp1075abp100g 100 13.5 400 disabled pdip8 (less pin#6) ncp1075bbp065g 65 13.5 400 disabled pdip8 (less pin#3) ncp1075bbp100g 100 13.5 400 disabled pdip8 (less pin#3) ncp1075bbp130g 130 13.5 400 disabled pdip8 (less pin#3) ncp1076abp065g 65 4.8 650 disabled pdip8 (less pin#6) ncp1076abp100g 100 4.8 650 disabled pdip8 (less pin#6) ncp1076bbp065g 65 4.8 650 disabled pdip8 (less pin#3) ncp1076bbp100g 100 4.8 650 disabled pdip8 (less pin#3) ncp1076bbp130g 130 4.8 650 disabled pdip8 (less pin#3) ncp1077abp065g 65 4.8 800 disabled pdip8 (less pin#6) ncp1077abp100g 100 4.8 800 disabled pdip8 (less pin#6) ncp1077bbp065g 65 4.8 800 disabled pdip8 (less pin#3) ncp1077bbp100g 100 4.8 800 disabled pdip8 (less pin#3) ncp1077bbp130g 130 4.8 800 disabled pdip8 (less pin#3) ncp1079abp065g 65 2.9 1050 disabled pdip8 (less pin#6) ncp1079abp100g 100 2.9 1050 disabled pdip8 (less pin#6) ncp1079bbp065g 65 2.9 1050 disabled pdip8 (less pin#3) ncp1079bbp100g 100 2.9 1050 disabled pdip8 (less pin#3) ncp1079bbp130g 130 2.9 1050 disabled pdip8 (less pin#3)
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 32 package dimensions pdip?7 (pdip?8 less pin 6) case 626a issue c 14 5 8 b2 note 8 d b l a1 a eb e a top view c seating plane 0.010 ca side view end view end view with leads constrained notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. dimensions a, a1 and l are measured with the pack- age seated in jedec seating plane gauge gs?3. 4. dimensions d, d1 and e1 do not include mold flash or protrusions. mold flash or protrusions are not to exceed 0.10 inch. 5. dimension e is measured at a point 0.015 below datum plane h with the leads constrained perpendicular to datum c. 6. dimension eb is measured at the lead tips with the leads unconstrained. 7. datum plane h is coincident with the bottom of the leads, where the leads exit the body. 8. package contour is optional (rounded or square corners). e1 m 8x c d1 b h note 5 e e/2 a2 note 3 m b m note 6 m dim min max inches a ???? 0.210 a1 0.015 ???? b 0.014 0.022 c 0.008 0.014 d 0.355 0.400 d1 0.005 ???? e 0.100 bsc e 0.300 0.325 m ???? 10 ??? 5.33 0.38 ??? 0.35 0.56 0.20 0.36 9.02 10.16 0.13 ??? 2.54 bsc 7.62 8.26 ??? 10 min max millimeters e1 0.240 0.280 6.10 7.11 b2 eb ???? 0.430 ??? 10.92 0.060 typ 1.52 typ a2 0.115 0.195 2.92 4.95 l 0.115 0.150 2.92 3.81
ncp1075a/b, ncp1076a/b, ncp1077a/b, ncp1079a/b www. onsemi.com 33 package dimensions pdip8 less pin 3 case 626as issue o 14 5 8 b2 note 6 d b l a1 a e a top view c seating plane 0.010 ca side view end view with leads constrained dim min max inches a 0.155 0.175 a1 0.020 0.040 b2 0.056 0.064 c 0.008 0.012 d 0.365 0.369 d1 0.005 0.080 e 0.100 bsc e 0.300 0.325 m ???? 10 3.94 4.45 0.51 1.02 1.42 1.63 0.20 0.30 9.27 9.37 0.13 2.03 2.54 bsc 7.62 8.25 ??? 10 min max millimeters notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. dimensions a, a1 and l are measured with the pack- age seated in jedec seating plane gauge gs?3. 4. dimensions d, d1 and e1 do not include mold flash or protrusions. mold flash or protrusions are not to exceed 0.10 inch. 5. dimension e is measured at a point 0.015 below datum plane h with the leads constrained perpendicular to datum c. 6. package contour is optional (rounded or square corners). e1 0.244 0.260 6.20 6.60 a3 0.015 bsc 0.38 bsc e1 m 7x c d1 b b 0.015 0.020 0.38 0.50 l 0.115 0.135 2.92 3.43 h note 5 e e/2 note 3 m b m m a3 end view on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp1076a/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?

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